High performance computers are required to transmit vast amounts of data, which requires high throughput and low error rates at low latency. High-speed signaling at 25 Gbps (gigabits per second) and higher per lane may result in a significant increase in bit error ratio due to interconnect imperfections and length-dependent signal loss. Previous approaches have improved the error ratio by using error correcting codes or packet replay. However, as speeds increase, these conventional techniques increase the latency data transmission through the system. There exists a need for error correction techniques to enable data transmission over long length channels, which operate at a higher bit error ratio, while maintaining low latency.